This invention relates generally to a semiconductor memory device, and more particularly to an improvement in a memory cell used for storing information in a dynamic type MOS memory.
A dynamic MOS memory forming one memory cell by one transistor has been known in the past. FIG. 1 of the acbompanying drawings illustrates the construction of such a memory cell. The memory cell consists of a capacitor (C.sub.MC) 1 for storing charge and an MOS transistor 2 for switching. The drain of this transistor is connected to a data line 3 and its gate is connected, to a word line 4. One of the ends of the capacitor is connected to the source of the MOS transistor with the other end being connected to a plate 5 which applies a predetermined potential (e.g. power source voltage V.sub.cc) to form the capacitance.
FIG. 2 schematically illustrates part of a memory cell array. A dummy cell (DC) 6 (6.sub.n, 6.sub.n) has a function of generating a reference signal when a delicate read signal from a memory cell (MC) 7(7.sub.n, 7.sub.n) is differentially amplified by a signal detector (sensor amplifier; SA) 8. The memory cell array has a construction such that when the memory cell 7.sub.n connected to either one of a pair of data lines (D.sub.n, D.sub.n)3.sub.n, 3.sub.n is selected, for example, to the word line (W) 4.sub.m on the side of 3.sub.n, by a word line driving pulse .phi.w from an address decoder (not shown), the dummy cell 6.sub.n connected to the dummy word line (DW) 9 on the other side 3.sub.n is selected by a dummy word line driving pulse .phi..sub.DW. In the drawing, reference numeral 10 represents a dummy memory cell clear line through which a pulse signal .phi..sub.p for discharging the dummy cell capacitor C.sub.DC 11 to a predetermined potential, e.g., to a ground potential, is applied. Reference numeral 12 represents a switching MOS transistor constituting the dummy cell, and reference numeral 13 does a clear MOS transistor. The dummy cell capacitor C.sub.DC 11 is interposed between the MOS transistor 12 and a plate 14 for applying a predetermined potential, in the same way as the memory cell capacitor C.sub.MC 1 described above.
In the circuit construction shown in FIG. 2, the reference signal by the dummy cell is set to the almost intermediate level between a "1" read signal and a "0" read signal from the memory cell, so that the capacitors C.sub.MC 1 and C.sub.DC 11 of the memory and dummy cells are set so as to satisfy the relation C.sub.DC .perspectiveto.1/2C.sub.MC.
The memory and dummy cell capacitors C.sub.MC, C.sub.DC are formed generally by diffusion layer type capacitors or gate oxide film capacitors of MOS transistors, and their values are proportional to the area of the region that forms the capacitance. To obtain the relation C.sub.DC .perspectiveto.1/2C.sub.MC, therefore, the area of the region that forms the dummy cell capacitor is set to be substantially the half of the area of the region that forms the capacitor of the memory cell. (This arrangement is disclosed in U.S. Pat. No. 3,678,473, for example.)
FIG. 3 shows in a plan view an example of a memory cell 7 using an n-channel MOS transistor. FIG. 4 is a sectional view taken along line A --A of FIG. 3. Among an active region 16 encompassed by a thick field oxide film 15 of at least 100 nm, a region 17 which is below a plate 5 made of polycrystalline Si and in which a gate oxide film consisting of silicon dioxide generally forms the memory cell capacitor. The plate 5 is selectively removed at the portion at which the switching MOS transistor is to be formed and at the portion of a contact hole 18 which connects the drain on the Si substrate with the data line 3. The word line 4 represented by polycrystalline silicon, molybdenum silicide or refractory metal (Mo and W) is deposited to the portion, forming the switching MOS transistor 2. In FIG. 4, reference numeral 19 represents a p-type Si substrate; 21 is a first inter-layer insulating film formed by oxidizing the polycrystalline Si plate 5; 22 is a second interlayer insulating film consisting of P-containing PSG which is formed by a so-called "CVD" process; and 23 is an n.sup.+ diffusion layer formed by implanting P or As to the silicon substrate. The switching MOS transistor 2 is formed by 23A and 23B.
The dummy cell 6 has the same construction as the memory cell 7, but due to the relation C.sub.DC .perspectiveto. 1/2c.sub.MC described above, the area of the region forming the dummy cell capacitor C.sub.DC is the half of the area of the region 17 forming the memory cell capacitor C.sub.MC.
To simplify the illustration, FIG. 5 shows only the region that forms the capacitor. In order to have the description more easily understood, the drawing shows the case in which the region forming the capacitor is square. FIG. 5a shows the region 24 that forms the dummy cell capacitor C.sub.DC and FIG. 5b shows the region 17 that forms the memory cell capacitor C.sub.MC. In view of the relation C.sub.DC .perspectiveto.1/2C.sub.MC described above, these regions 24 and 17 are determined so as to satisfy the relation L.sub.D .times.L.sub.D =(1/2(L.sub.M .times.L.sub.M) where L.sub.D .times.L.sub.D is the area of the region 24 and L.sub.M .times.L.sub.M is the area of the region 17. Here, L.sub.D and L.sub.M are dimensions after finish.
It has been clarified, however, that the prior art techniques described above cause the following critical problem due to the miniaturization of the memory cell pattern which is brought forth as a result of the increase of the scale of the memory capacity in recent years.
In other words, the miniaturization of the memory pattern limits the area allowed for the formation of the memory cell capacitor C.sub.MC to an extremely small value. The dummy cell capacitor C.sub.DC must be formed in a further smaller area because of the afore-mentioned relation C.sub.DC .perspectiveto.1/2C.sub.MC. Accordingly, they must be designed in a size which is close to the minimum possible limit of photoetching techniques used for the production process of semiconductor devices. Since the fabrication word is carried out in a region close to its limit, the variance of work is extremely great, and it becomes difficult to constantly keep the relation C.sub.DC .perspectiveto.1/2C.sub.MC.
The problem with the prior art techniques will now be described with reference to FIG. 5. If the change quantity of the finish size due to the work variance is .DELTA.L, the area (S.sub.DC) of the region 25 for forming the dummy cell capacitor C.sub.DC becomes (L.sub.D -.DELTA.L).times.(L.sub.D -.DELTA.L), and the area (S.sub.MC) for forming the memory cell capacitor C.sub.MC becomes (L.sub.M .times..DELTA.L) .times.(L.sub.M -.DELTA.L). Accordingly, the ratio of S.sub.DC to S.sub.MC becomes as follows: ##EQU1## Due to .DELTA.L, it becomes difficult to constantly keep the relation S.sub.DC .perspectiveto.1/2S.sub.MC, that is C.sub.DC .perspectiveto.1/2C.sub.MC, and this becomes a critical problem for the operation of the memory.
The reduction of L.sub.D means the increase of the ratio .DELTA.L/L.sub.D and becomes a problem to be solved in order to accomplish the miniaturization of the memory.